1. Field of the Invention
This invention relates to a process for manufacturing a semiconductor device. In particular, it relates to a process for manufacturing a semiconductor device using a damascene method where an interconnection is formed by burying an interconnection metal in a groove on an insulating layer, especially a copper damascene. This invention also relates to an exposure mask optimized for the process.
2. Description of the Related Art
Aluminum has been frequently used as an interconnection layer in a semiconductor device. However, it has been recently proposed to use Cu exhibiting a lower resistance as an interconnection material, and in some cases, it has been practically used.
Due to difficulty in dry-etching copper, photolithography cannot be used for patterning the copper interconnection as is in a conventional aluminum interconnection. Therefore, the copper interconnection is generally formed by burying copper in a groove on an interlayer insulating film and then flattening the surface(a damascene method).
In a common process for manufacturing a semiconductor device a plurality of semiconductor devices is simultaneously formed on a single wafer, and then divided into individual semiconductor device. A wafer has increasingly become larger particularly for reducing a cost. Now, a wafer with a diameter of 200 mm is commonly used, and a mounting technique to a wafer with a diameter of 300 mm is going to be established.
Such a trend holds true for forming a buried interconnection such as a copper interconnection. Specifically, copper is buried in a groove by forming a groove pattern for burying copper on a sheet of wafer; forming a barrier metal layer and a seed metal layer by spattering; depositing a thick copper layer by an appropriate technique such electrolytic plating; and then flattering the surface.
A groove pattern is formed by forming an insulating layer such as a silicon oxide film on, for example, a silicon wafer; applying a photoresist on the insulating film; exposing and developing an individual wafer to form a resist pattern; and etching the insulating layer by anisotropic etching such as dry etching using the resist pattern as a mask.
In the process, an exposure pattern has been formed by exposing the wafer using a mask corresponding to an interconnection pattern(the first mask 2) in an area of the wafer 1 where devices can be taken to form the interconnection pattern while using a mask such as a ground glass without a pattern(a blank mask 4) in the periphery of the wafer where devices cannot be taken for no-pattern exposure(i.e., exposure leaving no resist patterns) as illustrated in FIG. 6, or exposing the whole surface of the wafer using only the first mask 2 corresponding to the above interconnection pattern to form only the interconnection pattern as illustrated in FIG. 7.
FIGS. 8 and 9 are process cross-sections illustrating a wafer edge during forming a copper interconnection, where the whole surface is exposed using the first mask corresponding to an interconnection pattern. Herein, a case where the first interconnection layer is made of copper will be described.
An insulating film 102 is deposited on a silicon substrate 101 having a transistor(unshown) and a contact hole(unshown) (FIG. 8(A)). On the film is deposited a stopper film 103 such as an SiN film to a thickness of about 50 nm, on which is then deposited a flat insulating film 104 consisting of a silicon oxide to a thickness of about 400 nm for forming a groove in which copper is to be buried. On the film, a positive photoresist is applied. Then, the surface is exposed using only the mask having the reversed interconnection pattern as illustrated in FIG. 7 and developed to leave a resist pattern in the exposed area(unshown). The flat insulating film 104 is etched using the resist pattern as a mask to form a groove pattern as shown in FIG. 8(B).
Then, the substrate having the groove pattern is placed in a spattering equipment. On the substrate are deposited by spattering a barrier film 105 consisting of a high-melting metal nitride such as TaN to about 20 nm and then a Cu film 106 to about 100 nm. During the process, the periphery of the wafer is held by a clamp 107 as shown in FIG. 8(C) for preventing the materials from going around to the rear face of the wafer. The clamp 107 covers the periphery to about 3 mm from the wafer edge, and has an overhang-eaves end for preventing the clamp from being connected with the substrate via the material deposited by spattering.
As illustrated in FIG. 9(A), copper particles 108 splashed during depositing copper adhere to the area under the end eaves of the clamp. The adhering copper particles 108 are significantly fewer adherents to the base layer than the Cu film 106 deposited by spattering.
Then, copper is deposited by an appropriate technique such as electrolytic plating to a thickness of 800 nm, during which plated copper 109 grows around the adhering copper particles 108 and finally is joined with the plated copper 109 deposited on the spattered copper film 106 (FIG. 9(B)).
Subsequently, the plated copper 109, the spattered copper 106 and the barrier film 105 are polished by CMP until the surface of the groove oxide film 104 is exposed, the surface is flattened, and thereby copper is buried in the groove.
However, since the plated copper 109 around the copper particles 108 is less adhesive, peeling may occur during the CMP process as shown in FIG. 9(C). Then, the peeled part may be separated when the wafer is reloaded on a wafer carrier to adhere to an area between interconnection patterns, causing interconnection short-circuit, or some peeled parts may adhere to the wafer carrier, leading to contamination of other wafers. These problems may be more prominent when exposing the periphery shown in FIG. 6 without a pattern.
Furthermore, the larger a wafer is, the longer the peripheral length of the wafer is and thus the more frequent the problems occur.